This invention relates to an effective address producing and storing apparatus or arrangement supplied with an indirect designation effective address processing instruction for producing a succession of a plurality of effective addresses comprising first, second, and third effective addresses and for successively storing the first through third effective addresses in a buffer memory of a configuration which includes an information processing system comprising a main memory, a reading apparatus or arrangement, and the buffer memory.
The buffer memory is used in administering an addressing exception which occurs when the reading arrangement attempts to access an unavailable location of the main memory. The unavailable location is equivalent in meaning to a location which is not available in the configuration.
The main memory is for memorizing an operand datum at an operand address, a direct designation data descriptor at a direct descriptor address, and an indirect designation data descriptor at an indirect descriptor address. The direct designation data descriptor comprises a direct designation indicating portion and a direct designation address portion representative of the operand address. The direct designation indicating portion indicates direct designation for the operand datum. The indirect designation data descriptor comprises an indirect designation indicating portion and an indirect descriptor address portion representative of the direct descriptor address. The indirect designation indicating portion indicates indirect designation for the operand datum.
The indirect designation effective address processing instruction comprises an indirect designation indicating code and a source address section representative of the indirect descriptor address. The indirect designation indicating code indicates indirect designation for the operand datum.
A conventional effective address producing and storing apparatus or arrangement comprises an instruction register having first and second instruction register areas for memorizing the indirect designation indicating code and the source address section. Connected to the second instruction register area, a source address processing circuit processes the source address section into a source accessing signal representative of the indirect descriptor address.
Connected to the source address processing circuit, an effective address register memorizes the source accessing signal as the first effective address and uses the source accessing signal in making the reading arrangement access to the indirect descriptor address and read the indirect designation data descriptor as a first read-out data descriptor. The effective address register is connected to the buffer memory. Connected to the buffer memory, a storing circuit stores the first effective address in a first part of the buffer memory.
A descriptor register is connected to the indirect descriptor address of the main memory. The descriptor register has first and second descriptor register areas for memorizing, as a first designation indicating portion and a first designation address portion, the indirect designation indicating and the indirect descriptor address portions, respectively, which are had by the indirect designation data descriptor read as the first read-out data descriptor.
Connected to the second descriptor register area and the effective address register, an updating circuit updates the effective address register to make the effective address register memorize the first designation address portion as the second effective address instead of the first effective address. The effective address register thereby uses the first designation address portion in making the reading arrangement access to the direct descriptor address and read the direct designation data descriptor as a second read-out data descriptor. The storing circuit stores the second effective address in a second part of the buffer memory.
The descriptor register is furthermore connected to the direct descriptor address of the main memory. The descriptor register memorizes, as a second designation indicating portion and a second designation address portion instead of the first designation indicating and the first designation address portions, the direct designation indicating and the direct descriptor address portions, respectively, which are had by the direct designation data descriptor read as the second read-out data descriptor.
The updating circuit updates the effective address register to make the effective address register memorize the second designation address portion as the third effective address instead of the second effective address. The effective address register thereby uses the second designation address portion in making the reading arrangement access to the operand address and read the operand data. The storing circuit stores the third effective address in a third part of the buffer memory.
Thus, the conventional effective address producing and storing arrangement successively stores the first through the third effective addresses in the first through the third parts of the buffer memory, respectively. Thereafter, supplied with another indirect designation effective address processing instruction, the conventional effective address producing and storing arrangement produces another succession of a plurality of effective addresses and successively stores the effective addresses in different parts of the buffer memory that are different from the first through the third parts of the buffer memory.
The conventional effective address producing and storing arrangement is operable in cooperation with the information processing system in a pipeline fashion of first, second, third, and several subsequent pipeline stages. The first pipeline stage is carried out by the instruction and the descriptor registers. The second pipeline stage is dealt with by the effective address register. The third pipeline stage is carried out by the buffer memory. The subsequent stages are dealt with by the reading arrangement and the main memory.
Inasmuch as the conventional effective address producing and storing arrangement produces a succession of a plurality of effective addresses in accordance with the indirect designation effective address processing instruction and successively stores the effective addresses in different parts of the buffer memory and inasmuch as each of the effective addresses is typically thirty-one bits long, an overflow of the effective address which should be stored in the buffer memory, is liable to occur in the buffer memory when the conventional effective address producing and storing arrangement is supplied with the indirect designation effective address processing instruction which makes the conventional effective address producing and storing arrangement produce an increased number of the effective addresses. The overflow causes the pipeline of the information system to become clogged and degrades performance of the information processing system. In particular, the overflow makes it impossible to accurately deal with the addressing exception which occurs at the subsequent pipeline stages immediately after the overflow occurs. This is because the effective address in question overflows and is not perfectly stored in the buffer memory.
To avoid the overflow, another conventional effective address producing and storing apparatus or arrangement comprises another storing circuit which successively stores a plurality of the effective addresses in a same part of the buffer memory. That is, only a trailing one of the effective addresses remains in the buffer memory for each of the indirect designation effective address processing instructions. The trailing one of the effective addresses is equivalent to the direct designation address portion representative of the operand address. When an addressing exception occurs at the subsequent pipeline stages immediately after the trailing one of the effective addresses is stored in the buffer memory, operation of the information processing system is terminated for the trailing one of the effective addresses in question in a manner known in the art. It will be supposed that the trailing one of the effective addresses and a preceding effective address immediately preceding the trailing one of the effective addresses are necessary as an exception address and a preceding factor address, respectively, in processing the addressing exception in the information processing system which operates under the control of exception processing firmware with reference to the buffer memory. The exception address is equivalent in meaning to an effective address at which the addressing exception occurs and which designates the operand address. The preceding factor address is equivalent in meaning to another effective address which precedes the exception address and which designates the direct description address. In this case, the information processing system cannot deal with the addressing exception. This is because the preceding effective address does not remain in the buffer memory as the preceding factor address.